In keeping pace with progress in the fine machining technology in the manufacture of semiconductor devices, the tendency is towards higher integration and higher speed of semiconductor devices, in particular the complementary insulated gate semiconductor devices (CMOS). For coping with this tendency, the driving power source is becoming lower. That is, while the power source of 5 V is routinely used, a composite transistor device partly incorporating built-in MOS transistors of a power voltage system with 3.3 V or 2.5 V or less is currently manufactured.
In such MOS transistors, it is necessary to form an element with a different film thickness of a gate insulating film because of the difference in the gate withstand voltage or in order to obtain desired electrical properties. Since the gate insulating films need to be of different film thicknesses, it is necessary to implant ions separately from one element of a given sort to another to control the concentration of impurities.
In a semiconductor integrated circuit, transistors having a ROM function for outputting specified output signals to a given input signal are occasionally assembled. In this case, it is necessary additionally to form resists or implant ions in order to constitute a ROM. Referring to the drawings, the producing method for a semiconductor device constituted by transistors having different film thicknesses of gate insulating films and the ROM function is explained.
FIG. 1 is a cross-sectional view for illustrating the structure of a CMOS transistor of a dual power source system having an added ROM function, whilst FIGS. 11 to 13 are cross-sectional views for schematically illustrating the conventional producing process for this sort of the semiconductor device. Meanwhile, FIGS. 11 to 13 show a sequence of the producing process, step-by-step, which process steps represent one sequence of the producing process, although shown split in three figures.
Referring first to FIG. 11(a), a diffusion layer area on a p-type silicon substrate 1 is divided by an isolation oxide film 2 by LOCOS, and an oxide film 3 is formed for surface protection. It is noted that areas A, B and C, indicated on top of FIG. 11(a), denote transistor forming regions. Specifically, A, B and C denote a thin film transistor area having a thin-film gate oxide film, a thick-film transistor area having a thick gate oxide film, and a ROM code transistor area, respectively. Here, explanation is made of the case of forming a thin-film N-channel MOS transistor as a ROM code transistor.
Then, as shown in FIG. 11(b), a first resist pattern 4a, which lays open an N-channel of the thin-film transistor (the left side of the area A) and the ROM code transistor, is formed, and ions, such as B+ (boron) are implanted plural times to form P wells 6 in the p-type silicon substrate 1, whilst a threshold value of the thin-film N-channel transistor is determined.
Then, ions are implanted to form wells of the P-channel of the thin-film transistor, and N and P channels of the thick-film transistor. As ion species, As+ (arsenic) or P+ (phosphorous) is used for the P-channel, whilst B+ (boron) is suited for the N-channel (see FIGS. 11 (c) to 12 (e)).
Then, a fifth resist pattern 4e, laying open only the ROM code transistor, as shown in FIG. 12(f), is formed, and P+ ions are implanted to form an inversion layer 13 on a surface region, to complete the formation of wells of the five MOS transistors. Then, as shown in FIG. 12(g), the oxide film 3, formed at step (a), is removed, and a gate oxide film 9 is formed on the entire substrate surface by a thermal oxidation method (see FIG. 12(h)).
Then, for adjusting the film thickness of the gate oxide film, a sixth resist pattern 4f, which has laid open only a thin-film transistor region (area A), and a ROM code transistor region (area C), is formed, as shown in FIG. 13i, and the gate oxide film 9 in the opened area is etched off. Then, a gate oxide film 10 of a film thickness matched to the thin film transistor is formed by a thermal oxidation method (see FIG. 13(j)). At this time, the gate oxide film 9 of the area B is additionally oxidized and increased in film thickness so as to be thicker than the gate oxide film 10. A gate electrode 11 then is formed to complete a basic structure of the above-described semiconductor device.